(1) Field of the Invention
The present invention relates to a thin film transistor, and more particularly to a thin film transistor device so formed as to have a predetermined array on a substrate, which is used for a liquid crystal display and the like device, and a producing method thereof.
(2) Description of the Prior Art
In recent years, liquid crystal displays have been widely used for equipment for multi-media systems, portable electronic products, and communication devices. In such liquid crystal displays used for the electronic equipment as above, a requirement for a higher resolution has been growing. In other words, a smaller pixel size and higher performance are increasingly required.
Particularly, in a liquid crystal display panel using a thin film transistor (TFT), size reduction of a pixel part and the TFT composing the driving circuit thereof has been developed.
FIG. 1 shows an example of a structure of a thin film transistor known as a top gated type, used for the pixel part.
As shown in the figure, an SiO.sub.2 film 2 as an undercoat is formed on a glass substrate 1, and a semiconductor layer (material) 3 consisting of silicon poly-crystallized by laser annealing is provided thereon. A gate insulating film 5 is formed in a position that forms a channel, a gate electrode is provided thereon, and an interlayer dielectric layer 7 is formed thereover. The interlayer dielectric layer serves to prevent a contact between a source and drain electrode lines and the semiconductor layer in each of a large number of transistors formed on the substrate, and to prevent a short circuit of the transistors and pixel electrodes.
In a channel region, which is a region disposed between a source electrode and a drain electrode, a contact hole 9 is provided in the interlayer dielectric layer 7 at each of the outward end portions of the channel region, so as to reach the semiconductor layer 3, and a source electrode 10 and a drain electrode 11, both composed of a metal, are provided therein.
In portions 31 and 32 of the semiconductor layer 3 that are to be in contact with the source electrode 10 and the drain electrode 11 respectively, impurity atoms with three valences or five valences are doped by ion doping and the like method to reduce the resistance of the surface portion thereof.
This is intended to reduce a contact resistance by greatly lowering the electric barrier generated in the contact of the semiconductor layer and a metal layer.
However, in the structure shown in FIG. 1, such problems as described below are induced in cases where size reduction of TFTs and panel size increase are further advanced.
Firstly, a problem regarding a construction of the TFT is described below. As the size reduction of the TFT advances, the contact area between a semiconductor layer and a metal layer is also rendered small. Inversely, a contact resistance is rendered larger. The contact resistance greatly affects a driving capability of a thin film transistor, and as the value of the contact resistance is larger, the driving capability of the TFT is degraded. In consequence of future size reduction of TFTs and hence increasing tendency of such a disadvantageous effect as described above, it is expected to cause a failure to operate transistors located distant from a signal supply, thereby a failure to sufficiently charge pixels, and thus a failure to obtain a picture image.
Secondly, a problem regarding the fabrication, namely, a difficulty involved in forming a contact hole is described below with reference to FIG. 2.
(a) A gate insulating film 5 is formed on a poly-crystallized semiconductor thin film 3, and a gate electrode is formed on the gate insulating film 5. An interlayer dielectric layer 7 is formed over the gate insulating film 5 and the gate electrode 6.
(b) A contact hole is opened to form a source electrode and a drain electrode. As the size reduction of TFTs advances, a diameter of the contact hole is expected to be smaller. For example, it is currently smaller than 10 .mu.m, but a diameter of several micrometers is expected in recent years and even approximately 1 .mu.m will be desired. Forming such a small contact hole by wet etching is difficult in respect of obtaining an accurate diameter size (an error of about 2 .mu.m or 3 .mu.m is inevitable not only at present but in the near future), and therefore dry etching is employed.
In order to perform such dry etching, first, a resist pattern 8 with an aperture 80 is formed. The aperture 80 is opened in a region where each electrode is to be formed.
(c) A portion of the interlayer dielectric layer and the gate insulating film is removed with the use of an etching gas 21. The etching gas 21 used here is for example a mixed gas of CF.sub.4 and CHF.sub.3 and O.sub.2 and reactive ion etching (RIE) is performed therewith.
The gas to be used in the etching is a gas used for etching Si type material including Si--Ge and Si--Ge--C, and is capable of etching both Si and oxide films such as an interlayer dielectric layer and a gate oxide film. Therefore, in making a contact hole to form a source electrode and a drain electrode, a condition that a selective ratio of Si and the oxide film is rendered high (that the oxide film is more readily etched) should be met. However, at present or even in the near future, it is difficult to meet such a condition that only the oxide film is completely etched away and Si is left unetched, since both substances have similar chemical characteristics.
Accordingly, in order to completely etch away portions of the oxide films 5 and 71, formed as the interlayer dielectric layer and the gate insulating film underneath the contact hole, in an entire area of the substrate, the semiconductor layer (Si) under the contact hole needs to be slightly etched as well.
However, according to a recent requirement for the size reduction of TFTs, as well as such requirements that an amorphous silicon is fused and recrystallized on a glass substrate by laser irradiation and a crystal with as large a crystal grain as possible, preferably a single crystal, is desired in the step, the thickness of the semiconductor layer tends to be further reduced to 1000 .ANG. or less, preferably 300-600 .ANG., specifically approximately 500 .ANG..
Hence, in etching the oxide films, if a thickness variation of the oxide films and an etching rate variation are large, the semiconductor layer is excessively etched, and as a result, as shown in FIG. 2(d), the semiconductor layer is made too thin or in a severe case completely removed in a portion 30. Even if not made too thin, the semiconductor layer is damaged in a region underneath the contact hole and therefore a formation of a high resistance layer 33 can be induced.
When such disadvantageous effects as above are caused, a contact resistance between the semiconductor layer and the source or drain electrode is rendered too high, or even non-conductive state is incurred, and thus a good contact cannot be obtained. Such problems are critical in consideration of recent size increase of liquid crystal display panels, and size reduction and number increase of TFTs in line with the increase of pixel density.
However, at present or even in the near future, it would be difficult to increase the thickness of the semiconductor layer or to employ other gases only for an insulating material that has an advantageous effect.
In addition, such problems are induced also in a bottom-gated transistor.
Accordingly, a development of a TFT and its producing method is desired in which a contact resistance is suppressed low even when the device size is reduced, and etching for making contact holes is readily performed.